AMD port microblog :-)

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mrb
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Re: AMD port microblog :-)

Post by mrb » Sun Nov 02, 2008 6:22 am

Aaah, a simple answer to a simple question. Thanks ! And yes I think proper terminology is important.

I am sure if you disassemble this person's MD5 IL cracker you will notice it fails to fully exploit the 5-way VLIW parallelism, explaining the performance inferior to the theorized 1400-1500 Mhash/s.

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BarsMonster
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Re: AMD port microblog :-)

Post by BarsMonster » Sun Nov 02, 2008 10:21 am

mrb wrote:fails to fully exploit the 5-way VLIW parallelism
Hmm... Isn't AMD clever enough to pack 5 threads to 1 VLIW instruction?

mrb
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Re: AMD port microblog :-)

Post by mrb » Sun Nov 02, 2008 9:40 pm

Yeah but depending on how the IL code is written, the CAL compiler might have a hard time to translate the IL code to VLIW instructions that always use the 5 thread processors.

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