Re: Learning ASIC design

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Learning ASIC design

Post by BarsMonster » Sat Apr 30, 2011 5:37 pm

If you would teach me about ASIC design (Cadence/Mentor/Free tools) and/or manufacturing process - I would be able to tapeout several projects of your students/you to return the favor (in any case, if project succeed I am going to tapeout selected student projects to promote ASIC design). Just imagine - they could design a CPU and get it working in their hands, and it's not FPGA cheat :-) Just like old good 80's when universities were designing CPUs :crazy:

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Re: Learning ASIC design

Post by #E0 » Tue May 03, 2011 12:23 pm

Regarding CAD tools and data.
On the first step we should get:
1. Cadence IC package of any version, 6.x is preferable. I'm aware of hacked version.
This is a minimum to design layout of transistors and simple CMOS gates like inverter, NAND and NOR
(I can take care of technology file necessary for layout entry.)
On this step we can prepare masks for "p" and "n" types transistors.
We can make test chip to measure transistor's characteristics, tune-up the process and start create model-file.

For more sophisticated IC development we will need:
Spectre (Cadence Simulator, part of IC package) model files. (Never looked inside of them, but I can get reference in any time)
2. Mentor Graphics Calibre tool for physical verification (DRC/LVS). We need to create DRC and LVS decks.
On this step we can produce simple digital design like shift-register or so.

To create digital IC of any feasible size we will need:
1. Cadence Encounter (the later version the better)
If we create standard cells library and Technology LEF-file, we can generate any digital layout using the scheme's behavioral Verilog.

From your side you should:
1. Setup dedicated Linux machine, with any RDP server. Consider screen's refresh rate in GUI mode #1 priority. Compatibility with Apple Mac machine #2.
2. Obtain hacked tool versions.
3. Setup them.

From my side I can try to help with tools installation. Provide training sessions with tools. Design layouts, schematics.

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Re: Learning ASIC design

Post by BarsMonster » Wed May 04, 2011 3:24 am

Thanks for detailed plan, looks awesome, starting on my side now.

Meanwhile, leaving 2 links I've found while reading about standard cell libs

http://www.vlsitechnology.org/ - awesome article about performance vs cell size library (http://www.vlsitechnology.org/html/cell_choice2.html)
http://www.vlsitechnology.org/html/libraries.html - overview of various open cell libraries
http://www.hpc.msstate.edu/mpl/educatio ... loads.html - some simple standard cell library, verified in silicon.

Still impressed how this synthesis software generates various schemes out of this "randomly-chosen" set of standard cells. I was expecting them to be way dumber.

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Re: Learning ASIC design

Post by DavidCary » Tue Mar 13, 2012 9:56 pm

Many years ago, I used MAGIC at school to design some very simple digital circuits.
(Alas, mine never got past the simulation stage, but I hear that some students used MAGIC to design entire chips that were later fabbed by MOSIS).

I've been collecting a list of IC layout tools (including links to download MAGIC) and some ideas that people have for making them better.
http://david.carybros.com/html/vlsi.html#design
http://david.carybros.com/html/ic_layout_tool.html
http://en.wikipedia.org/wiki/Magic_%28software%29

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