Character generation algorithm

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Corni
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Character generation algorithm

Post by Corni » Fri Dec 26, 2008 8:20 pm

Hi,
I'm currently programming an FPGA for hash cracking (MD4 for 160 bits input, optimized and pipelined runs at a speed of ~150MhZ, each clock a hash, without comparing and
input generating 5/clock) and I'm in search of a way to feed my hash routine with input. This should be mostly for mixedalphanumeric, and, highly critical, very parallel, as long sequential code sections limit the frequency at which I can run the FPGA. Also i've a problem with pipelining, the delivering of the right input to the right stage of the pipeline. How did you realize this (ensuring that each step in the pipeline gets the input it needs, and no other, and later, when the hash is found, getting the orginal input used to compute this hash...)?
Corni

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Re: Character generation algorithm

Post by BarsMonster » Fri Dec 26, 2008 8:58 pm

I was passing data via line of registers, they pass input value to the next one in line at each clk.
If you are going to do 1 key / clk, you will have to have a logic for each step, so the overall design would be rather large... What is your target FPGA chip?

Corni
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Re: Character generation algorithm

Post by Corni » Fri Dec 26, 2008 9:04 pm

I'm usnig a xilinx spartan 3-AN with 700K Gates. I thought about after posting, too (sometimes writing that stuff down relly helps!) and for passing the input's to the algorithm parts I came up with a multidimensional array, which is shifted each clk, so that one gets the input for the hash currently computed. This has the downside that for every input access i've to count the pipeline steps...
What did you for generating the input? just as much if's as you've characters and then counting? Or have you something better, which is more parallel?
Corni

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Re: Character generation algorithm

Post by BarsMonster » Fri Dec 26, 2008 9:34 pm

I had binary key, so there was a simple counter. I had logic for all steps at once, so I needed around 2mil gates for RC5 (which is not the same but similar).

Building key generation which would be able to generate 1 key (with a "carry") in 1 clk should be challenging (like several counters with comparators - it would take several clk to propagate carry)...
I guess divisor modules are not able to calculate mod in 1 clk?

Probably You can have several parallel generators working at clk/8 with a multiplexor or something like that.

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